Field of the Invention
The present invention relates generally to the field of computing, and more particularly to processor power management.
Background of the Related Art
Processor power management is an increasingly important strategy with the proliferation of computers. Reducing energy usage by processors provides many advantages, such as reducing costs, increasing component longevity and reducing heat production. For example, in a datacenter containing servers used in cloud computing, the energy required to power processors and attendant cooling systems may represent a significant operating expense. To reduce processor energy consumption, processor power usage mechanisms have been developed to dynamically control processor power usage.
Examples of some processor power usage mechanisms may include: dynamic voltage and frequency scaling (DVFS), processor core nap, and processor folding. Dynamic voltage scaling is a power usage mechanism where the voltage used in a processor can be increased or decreased dynamically. Dynamic frequency scaling is a power usage mechanism where the processor frequency can be increased or decreased dynamically. Lower voltage or lower frequency yields less power consumption by the processor. Processor core nap can be used to clock off most of the circuits inside a processor core when there is no work to be done by the core to save energy. This causes the core to go into a low-power idle state. Processor folding is a power usage mechanism where the number of available processor cores can be increased or decreased dynamically. Tasks are reallocated to the available cores and the other cores remain in low-power idle states.
These processor power usage mechanisms must be utilized to facilitate desired energy reduction goals. If, however, processor power usage mechanisms are aggressively used to reduce energy consumption, processor throughput may drop too low resulting in unacceptable task response time for a user.